The present disclosure relates generally to analysis of circuit designs, and more particularly to analyzing and ensuring proper functionality of lower power designs.
As the complexity in circuit design has increased, there has been a corresponding need for improvements in various kinds of analysis and debugging techniques. In fact, these analysis and debugging techniques have evolved from relatively simple transistor circuit-level simulation (in the early 1970s) to logic gate-level simulation (in the late 1980s) to the current art that uses Register Transfer Language (RTL)-level simulation, and formal verification. RTL describes the registers of a computer or digital electronic system and the way in which data are transferred among the combinational logic between registers.
Existing verification and debugging tools are used in the design flow of a circuit. The design flow begins with the creation of a circuit design at the RTL level using RTL source code. The RTL source code is specified according to a Hardware Description Language (HDL), such as Verilog HDL or VHDL. Circuit designers use high-level hardware description languages because of the size and complexity of modern integrated circuits. Circuit designs are developed in a high-level language using computer-implemented software applications, which enable a user to use text-editing and graphical tools to create a HDL-based design.
An important factor in many modern circuit design applications is reducing the amount of power consumed. Modern low-power circuit designs utilize power-domains to manage power to a group of logic in a circuit design. In order for this scheme to work, the interfaces between the different power-domains need to be modified to ensure error-free operation. Additionally, power domains that shut-off need to recover to a proper state when power is again provided.
Furthermore, sequential equivalence checking is typically performed on two circuits to determine that they are functionally equivalent at all times, i.e., given a set of input sequences, the output sequences match exactly. However, RTL descriptions of circuit designs do not contain power information causing failure of typical sequential equivalence checking since designs must be equivalent in all situations rather than only when power is provided in the power domains including outputs tested for equivalence. Thus, low power circuit designs cannot include some potentially power saving features while still passing verification testing to ensure proper functionality.